1. Field of the Invention
This invention relates to non-volatile flash-memory systems, and more particularly to management of overhead bytes and host interrupts.
2. Description of the Related Art
A traditional storage medium in computer systems is the hard disk. More recently hard disks are being replaced by non-volatile semiconductor memory. An array of non-volatile random-access memories (NVRAM's) or non-volatile flash memories substitutes for the hard-disk storage. These memory devices use electrically-erasable programmable read-only-memory (EEPROM) technology for storage cells. Floating polysilicon gates in these storage cells retain charge and state when power is lost, providing non-volatile storage. These flash-memory systems are frequently used as a mass-storage replacement for a hard disk on a personal computer and are thus sometimes referred to as a flash "disk", even though no rotating disks are used.
Flash-memory chips contain memory arrays of EEPROM cells that are arranged into blocks of pages. A 64 Mbit flash chip typically has 16-page blocks and 512-byte pages, which matches the sector size for IDE and SCSI hard disks. The entire page is written at the same time; individual bytes are not written. The page must be cleared of any previous data before being written; clearing is accomplished by a flash erase cycle. An entire block of pages (typically 16 pages) is erased at once. Thus a block of 16 pages must be erased together, while all 512 bytes on a page must be written together.
Each page contains a 512-byte data field and an additional 16-byte pointer or system-overhead field. The 16-byte overhead field has traditionally been used to store an address pointer to another flash-memory page. This pointer is used when the flash page has become worn out and has an error. The new page pointed to contains the replaced data.
The co-pending application, "Unified Re-Map and Cache-Index Table with Dual Write-Counters for Wear-Leveling of Non-Volatile Flash RAM Mass Storage", U.S. Ser. No. 08/918,203, described an address re-mapping table for use with a flash-memory system. This re-mapping table rather than the pointers in the overhead bytes is used for translation. All incoming addresses from a host are translated to physical block addresses of blocks within the flash memory. The re-mapping table also translates addresses away from faulty or worn flash-memory blocks.
By providing a unified re-mapping table that translates all incoming addresses, complex pointers do not have to be stored in the system-overhead bytes of a flash-memory page. Using block-level rather than page-level re-mapping also frees up more of the overhead bytes for use by an error-correction code (ECC). Having more bytes available for ECC allows for better, more effective codes that are able to correct more errors. These features improve performance and reliability.
Overhead Bytes Complicate System
Address management is complicated by the overhead bytes. Each 512-byte page must be expanded to 528 bytes to accommodate the 16-byte overhead field that is stored with the flash page. Since 528 bytes is not a power of 2, these enlarged pages are no longer aligned. Generation of the information in the overhead bytes and their formatting must also be performed. This generation and formatting ideally should be transparent to the host so that the host's performance is not degraded by formatting and non-aligned data transfers.
Flash-Specific DMA
The co-pending application, U.S. Ser. No. 08/939,601, disclosed an expandable flash-memory system. Flash-specific direct-memory access (DMA) controllers were used to transfer data from a DRAM cache to the flash-memory chips through buffer chips. These DMA controllers accepted block-level requests from a local processor. These block-level requests were translated by the DMA to a sequence of page-level commands that the flash-memory chips could accept.
Since blocks contain such a large amount of data, the host may wait for a relatively long time until the block of data is read from the flash-memory chips. Often the host is only interested in a small portion of the data in the block, such as the data on one of the 16 pages. Although the host may desire the data on the first or second page, the host must wait until all 16 pages of the block are read from the flash-memory chips and into the DRAM cache. Once all pages are read, then the host is notified that it can read the desired data. Using a write-back cache on a block basis requires that all pages in a block be read from the flash-memory chips.
It is desired to reduce the delay until the host can read data from a flash-memory system. It is desired to signal the host that the data is ready before the entire block of data has been read from the flash-memory chips. It is further desired to generate and format the overhead bytes of a flash page in a manner that is transparent to the host.